1. Field
Example embodiments relate to methods of manufacturing semiconductor devices. More particularly, example embodiments relate to methods of manufacturing vertical type semiconductor devices having high reliability by reducing a process defect ratio.
2. Description of the Related Art
An integrating method of cells along a vertical direction on a substrate accomplishes a high integration density of semiconductor devices. To manufacture vertical type semiconductor devices including a plurality of vertically integrated cells, a large number of thin layers may be integrated in a cell region and a height of a structure including the integrated cells and formed in the cell region may become large. Therefore, a height of channel layer patterns forming memory cells may be high to accomplish the high integration degree of the memory devices. In addition, a formation of the channel layer patterns having uniform heights may become difficult.
Further, a height of thin layers for forming circuits may be relatively low in a peripheral region when compared to the cell region. Accordingly, a thickness of a step difference between thin layers formed in the cell region and the peripheral region may become large. Due to the step difference formed between the thin layers formed in the cell region and the peripheral region, a large step difference may be formed in an insulating interlayer covering the thin layers in the cell region and the peripheral region. Although a polishing process may be performed with respect to the insulating interlayer, the insulating interlayer including a low step difference portion may not be completely removed because of the step difference formed in the insulating interlayer across the cell region and the peripheral region, thereby generating a residue defect. In addition, dishing may be generated in the insulating interlayer covering the low step difference portion.